`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:18:45 04/13/2009 
// Design Name: 
// Module Name:    piperegMEMWB 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module piperegMEMWB(in1, in2, in3, in4, clk, out1,out2,out3,out4);
    input [31:0] in1,in2,in4;
    input clk, in3;
    output [31:0] out1,out2,out4;
	 output out3;
	 	 
	 reg [31:0] out1,out2,out4;
	 reg out3;
	 
	 always @ (posedge clk)
	 begin
	 out1 = in1;
	 out2 = in2;
	 out3 = in3;
	 out4 = in4;
	 end
endmodule
